Method for repeated block modification for chip routing
US8407650B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2008 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Mar 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global router to wire through the repeated block. Buffers and associated pins can be inserted into repeated block within the flyover space where the global router wires to the needed buffer through area pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.