Rasmus Barringer
7Patents
4h-index
5Co-inventors
42Inventor score
Filing activity: Sep 22, 2010 → Mar 16, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8823736B2 | Graphics tiling architecture with bounding volume hierarchies | Physics | 56 | Active |
| US8593466B2 | Tile rendering for image processing | Physics | 6 | Active |
| US9501860B2 | Sparse rasterization | Physics | 5 | Active |
| US9928640B2 | Decompression and traversal of a bounding volume hierarchy | Physics | 4 | Active |
| US10600231B2 | Compressed bounding volume hierarchy | Physics | 3 | Active |
| US10134101B2 | Using cost estimation to improve performance of tile rendering for image processing | Physics | 0 | Active |
| US10049486B2 | Sparse rasterization | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.