Patent · US Active

Graphics tiling architecture with bounding volume hierarchies

US8823736B2 · kind B2 · utility

56Cited by

3References

51Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Rasmus Barringer · Helsingborg, SE
Carl Johan Gribel · Lund, SE
Aaron Eliot Lefohn · Bothell, US
Tomas G. Akenine-Moller · Lund, SE

Key dates

Filing date	Jan 20, 2012
Grant date	Sep 2, 2014
Priority date	—
Expiry date	Dec 9, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG09G2360/125
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In some embodiments, tile lists may be avoided by storing the geometry of a scene in a bounding volume hierarchy (BVH). For each tile, the bounding volume hierarchy is traversed. The traversals continued only into children nodes that overlap with the frustum on the tile. By relaxing the ordering constraint of rendering primitives, the BVH is traversed such that nodes that are closer to the viewer are traversed first, increasing the occlusion culling efficiency in some embodiments. Rendering the full scene between the central processing cores and the graphics processor may be done through a shared memory in some embodiments.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.