Shaojun Wei
23Patents
2h-index
30Co-inventors
53Inventor score
Filing activity: Nov 2, 2011 → Mar 7, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10705878B2 | Task allocating method and system capable of improving computational efficiency of a reconfigurable processing system | Physics | 13 | Active |
| US9734056B2 | Cache structure and management method for use in implementing reconfigurable system configuration information storage | Physics | 11 | Active |
| US10848306B2 | Method and system of implementing security algorithm and decryption algorithm by using reconfigurable processor | Electricity | 2 | Active |
| US10572671B2 | Checking method, checking system and checking device for processor security | Physics | 1 | Active |
| US9753878B2 | Extending the capabilities of existing devices without making modifications to the existing devices | Emerging Cross-Sectional Technologies | 1 | Active |
| US12039305B2 | Method for compilation, electronic device and storage medium | Physics | 1 | Active |
| US9729277B2 | Signal detecting method and device | Electricity | 1 | Active |
| US10684896B2 | Method for processing asynchronous event by checking device and checking device | Physics | 0 | Active |
| US11263314B2 | Processor checking method, checking device and checking system | Physics | 0 | Active |
| US10331381B2 | Method and device for recording memory access operation information | Physics | 0 | Active |
| US11822326B2 | Voter-based method of controlling redundancy, electronic device, and storage medium | Emerging Cross-Sectional Technologies | 0 | Active |
| US10564948B2 | Method and device for processing an irregular application | Physics | 0 | Active |
| US10657022B2 | Input and output recording device and method, CPU and data read and write operation method thereof | Physics | 0 | Active |
| US9632937B2 | Pre-decoding analysis based configuration information cache management method and system | Electricity | 0 | Active |
| US10310894B2 | Method and device for generating configuration information of dynamic reconfigurable processor | Physics | 0 | Active |
| US10956397B2 | Method and apparatus for processing concurrent transactions, and storage medium | Physics | 0 | Active |
| US10033526B2 | One INS network-based anti-fault attack method of random infection | Electricity | 0 | Active |
| US10217025B2 | Method and apparatus for determining relevance between news and for calculating relevance among multiple pieces of news | Physics | 0 | Active |
| US10203960B2 | Reconfigurable processor and conditional execution method for the same | Physics | 0 | Active |
| US10423795B2 | Method, checking device, and system for determining security of a processor | Physics | 0 | Active |
| US10642981B2 | Checking method, checking device and checking system for processor | Physics | 0 | Active |
| US10311017B2 | Reconfigurable processor and timing control method thereof | Physics | 0 | Active |
| US11062020B2 | Processor checking method, checking device and checking system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.