Shirish Kumar Agarwal
8Patents
1h-index
11Co-inventors
40Inventor score
Filing activity: Mar 13, 2014 → Dec 26, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9697124B2 | Systems and methods for providing dynamic cache extension in a multi-cluster heterogeneous processor architecture | Emerging Cross-Sectional Technologies | 3 | Active |
| US9244747B2 | System and method for providing dynamic clock and voltage scaling (DCVS) aware interprocessor communication | Emerging Cross-Sectional Technologies | 1 | Active |
| US9678809B2 | System and method for providing dynamic clock and voltage scaling (DCVS) aware interprocessor communication | Emerging Cross-Sectional Technologies | 1 | Active |
| US11363501B2 | Intelligent connectivity switching mechanisms | Electricity | 1 | Active |
| US9717051B2 | Proactive control of hardware based upon monitored processing | Emerging Cross-Sectional Technologies | 1 | Active |
| US9619014B2 | Suspend and resume timeline optimization for application processor | Emerging Cross-Sectional Technologies | 0 | Active |
| US9733694B2 | Apparatus, system and method for dynamic power management across heterogeneous processors in a shared power domain | Emerging Cross-Sectional Technologies | 0 | Active |
| US9671857B2 | Apparatus, system and method for dynamic power management across heterogeneous processors in a shared power domain | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.