Systems and methods for providing dynamic cache extension in a multi-cluster heterogeneous processor architecture
US9697124B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2015 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | May 30, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.