Inventor · Jericho, VT, US

Steven E. Charlebois

5Patents
3h-index
6Co-inventors
39Inventor score

Filing activity: Apr 30, 2004 → Feb 28, 2008

Most-cited inventions

PatentTitleAreaCited byStatus
US7444609B2 Method of optimizing customizable filler cells in an integrated circuit physical design process Physics 200 Active
US7539968B2 Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints Physics 9 Active
US7194715B2 Method and system for performing static timing analysis on digital electronic circuits Physics 8 Expired
US7873923B2 Power gating logic cones Physics 3 Active
US7886253B2 Design structure for performing iterative synthesis of an integrated circuit design to attain power closure Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.