Method of optimizing customizable filler cells in an integrated circuit physical design process
US7444609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2006 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Jan 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement algorithm performs the operation of selecting a starting point within a given circuit layout, selecting a direction in which the position of logic cells is adjusted, adjusting the position of logic cells and, thereby, combining filler cells in order to increase the accumulated area thereof; suspending the adjustment operation when a customizable filler cell is formed; and resuming the adjustment operation from the point of the newly formed customizable filler cell. Additionally, a method of optimizing the locations, number, and distribution of the customizable filler cells in an integrated circuit design by use of the filler cell placement algorithm is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.