Suresh E. Warrier
22Patents
6h-index
14Co-inventors
62Inventor score
Filing activity: Jul 20, 2000 → Dec 1, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6981243B1 | Method and apparatus to debug a program from a predetermined starting point | Physics | 25 | Expired |
| US7458076B2 | Method, apparatus, and computer program product for dynamically tuning a data processing system by identifying and boosting holders of contentious locks | Physics | 20 | Active |
| US8136111B2 | Managing execution of mixed workloads in a simultaneous multi-threaded (SMT) enabled system | Physics | 11 | Active |
| US7337444B2 | Method and apparatus for thread-safe handlers for checkpoints and restarts | Physics | 11 | Expired |
| US8261243B2 | Selective execution of trace mechanisms for applications having different bit structures | Physics | 9 | Active |
| US7117354B1 | Method and apparatus for allowing restarted programs to use old process identification | Physics | 6 | Expired |
| US8327368B2 | Managing execution of mixed workloads in a simultaneous multi-threaded (SMT) enabled system | Physics | 4 | Active |
| US7797706B2 | Method and apparatus for thread-safe handlers for checkpoints and restarts | Physics | 4 | Active |
| US7487347B2 | Method and apparatus for allowing restarted programs to use old process identifications and thread identifications | Physics | 3 | Active |
| US7380241B2 | Scalable and improved profiling of software programs | Physics | 2 | Active |
| US8843673B2 | Offloading input/output (I/O) completion operations | Physics | 1 | Active |
| US9229716B2 | Time-based task priority boost management using boost register values | Physics | 1 | Active |
| US9904580B2 | Efficient critical thread scheduling for non-privileged thread requests | Physics | 1 | Active |
| US7653910B2 | Apparatus for thread-safe handlers for checkpoints and restarts | Physics | 1 | Active |
| US8418152B2 | Scalable and improved profiling of software programs | Physics | 0 | Active |
| US9817696B2 | Low latency scheduling on simultaneous multi-threading cores | Physics | 0 | Active |
| US9798582B2 | Low latency scheduling on simultaneous multi-threading cores | Physics | 0 | Active |
| US9891956B2 | Efficient critical thread scheduling for non-privileged thread requests | Physics | 0 | Active |
| US10896065B2 | Efficient critical thread scheduling for non privileged thread requests | Physics | 0 | Active |
| US8874805B2 | Offloading input/output (I/O) completion operations | Physics | 0 | Active |
| US11010199B2 | Efficient critical thread scheduling for non-privileged thread requests | Physics | 0 | Active |
| US8032887B2 | Method and apparatus for allowing restarted programs to use old process identification | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.