Low latency scheduling on simultaneous multi-threading cores
US9817696B2 · kind B2 · utility
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3References
11Claims
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Key dates
| Filing date | Feb 24, 2016 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Feb 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/501
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.