Will Eatherton
1Patents
1h-index
4Co-inventors
25Inventor score
Filing activity: Feb 8, 2005 → Feb 8, 2005
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7551617B2 | Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor | Electricity | 16 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.