Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor
US7551617B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2005 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Nov 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network processor has numerous novel features including a multi-threaded processor array, a multi-pass processing model, and Global Packet Memory (GPM) with hardware managed packet storage. These unique features allow the network processor to perform high-touch packet processing at high data rates. The packet processor can also be coded using a stack-based high-level programming language, such as C or C++. This allows quicker and higher quality porting of software features into the network processor.Processor performance also does not severely drop off when additional processing features are added. For example, packets can be more intelligently processed by assigning processing elements to different bounded duration arrival processing tasks and variable duration main processing tasks. A recirculation path moves packets between the different arrival and main processing tasks. Other novel hardware features include a hardware architecture that efficiently intermixes co-processor operations with multi-threaded processing operations and improved cache affinity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.