Systems and methods of detecting errors during read operations and skipping word line portions
US10002042B2 · kind B2 · utility
6Cited by
14References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2015 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Apr 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The non-volatile memory includes a plurality of blocks and each block of the plurality of blocks includes a plurality of word lines. The controller is configured to receive data read from a word line of a block of the non-volatile memory and to determine an error indicator value based on the data. The controller is further configured to, responsive to the error indicator value satisfying a threshold, indicate that at least a portion of the word line is to be skipped during writing of second data to the block of the non-volatile memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.