Optimized depth buffer cache apparatus and method
US10002455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2015 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Apr 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are described for performing efficient depth test operations. For example, an apparatus in accordance with one embodiment comprises: a depth cache to store a plurality of cache lines containing depth data to be used for graphics processing operations; depth test logic to determine a current depth test function associated with a read operation and to read a cache line from a depth cache while there are still outstanding writes to the cache line if the read operation and write operation are associated with the same depth test function, the depth test logic to perform a first depth test using the data read from the cache line, the first depth test to fail or pass pixels based on a predicted range of depth values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.