Semiconductor devices
US10002651B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2017 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include a valid command generation circuit and a training control circuit. The valid command generation circuit may be configured to latch an internal chip selection signal and an internal control signal in synchronization with a division clock signal to generate a latch chip selection signal and a latch control signal. The valid command generation circuit may be configured to generate a valid command for executing a predetermined function from the latch control signal. The training control circuit may be configured to generate a training result signal from the latch chip selection signal or the latch control signal based on a flag.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.