Transistor gain cell with feedback
US10002660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2017 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Jun 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.