Alexander Fish
24Patents
5h-index
30Co-inventors
65Inventor score
Filing activity: Aug 27, 2003 → Nov 18, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8161427B2 | Logic circuit and method of logic circuit design | Electricity | 110 | Active |
| US7345511B2 | Logic circuit and method of logic circuit design | Electricity | 17 | Expired |
| US8280098B2 | Digital watermarking CMOS sensor | Electricity | 9 | Active |
| US7990451B2 | Optical pixel and image sensor | Electricity | 8 | Active |
| US8004316B2 | Logic circuit and method of logic circuit design | Electricity | 5 | Active |
| US8531873B2 | Ultra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation | Physics | 4 | Active |
| US7716625B2 | Logic circuit and method of logic circuit design | Electricity | 4 | Active |
| US10572619B2 | Pseudo-asynchronous digital circuit design | Physics | 4 | Active |
| US9691445B2 | Transistor gain cell with feedback | Electricity | 3 | Active |
| US8188767B2 | Logic circuit and method of logic circuit design | Electricity | 3 | Active |
| US8901965B2 | Device and method for dual-mode logic | Physics | 3 | Active |
| US10521530B2 | Data-dependent delay circuits | Physics | 2 | Active |
| US11586778B2 | Secured memory | Physics | 2 | Active |
| US10951391B2 | Randomized logic against side channel attacks | Electricity | 2 | Active |
| US11127455B2 | Fin-FET gain cells | Electricity | 1 | Active |
| US10497410B2 | High-density memory macro | Physics | 1 | Active |
| US9430598B2 | Dual mode logic circuits | Physics | 1 | Active |
| US11321460B2 | Information redistribution to reduce side channel leakage | Electricity | 0 | Active |
| US10002660B2 | Transistor gain cell with feedback | Electricity | 0 | Active |
| US10991421B2 | Complementary dual-modular redundancy memory cell | Physics | 0 | Active |
| US11023632B2 | Pseudo-asynchronous digital circuit design | Physics | 0 | Active |
| US12261600B2 | Method for mitigation of droop timing errors including a droop detector and dual mode logic | Physics | 0 | Active |
| US10169617B2 | Multi-topology logic gates | Physics | 0 | Active |
| US8773895B2 | Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.