Metal interconnect processing for a non-reactive metal stack
US10002774B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2017 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Sep 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit (IC) includes forming a metal interconnect stack on substrate that includes a plurality of product die each having a plurality of transistors connected together to implement a circuit function. The forming the metal interconnect stack includes depositing a metal interconnect layer comprising aluminum on a barrier layer at a first temperature. After depositing the metal interconnect layer, the metal interconnect stack is annealed in a non-oxidizing ambient at a maximum annealing temperature that is<the first temperature. After the annealing, a pattern is formed on the metal interconnect layer, and at least the metal interconnect layer is etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.