Power and ground routing of integrated circuit devices with improved IR drop and chip performance
US10002833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2017 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | May 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.