Stacked image sensor with embedded FPGA and pixel cell with selectable shutter modes and in-pixel CDs
US10002901B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2017 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Oct 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imaging system with a pixel cell has a photodiode, a transfer transistor, a reset transistor, an amplifier transistor in a source follower configuration, and a readout circuit block. The photodiode, transfer transistor, reset transistor and source follower amplifier are part of an array disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit block may be partially disposed within a second substrate of a second semiconductor chip and partially disposed within the first substrate wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling. The second semiconductor chip includes circuit elements to extract an image from the array and a Field Programmable Gate Array to provide reconfigurability to control and signal processing functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.