Space efficient and power spike resistant ESD power clamp with digitally timed latch
US10003191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2015 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Dec 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Embodiments include a system, apparatus, and method for ESD power clamps. Aspects include protecting a circuit using an ESD power clamp device. The ESD power clamp device includes a trigger circuit having a resistor-capacitor network and an inverter stage circuit, wherein the trigger circuit is configured to detect an ESD event. Aspects of the invention further include a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit controls the timing controlled transistor to prevent the capacitor in the RC network from charging when the timing circuit is initiated. Aspects also include a clamp transistor coupled to the trigger circuit, wherein the clamp transistor is controlled by a signal received from the trigger circuit, and a timing controlled transistor coupled to the trigger circuit and the timing circuit, where the timing controlled transistor switches states based on the output of the timing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.