Compact class-F chip and wire matching topology
US10003311B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2016 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Dec 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier circuit includes an RF input port, an RF output port, a reference potential port, and an RF amplifier having an input terminal and a first output terminal. An output impedance matching network electrically couples the first output terminal to the RF output port. A first inductor is electrically connected in series between the first output terminal and the RF output port, a first LC resonator is directly electrically connected between the first output terminal and the reference potential port, and a second LC resonator is directly electrically connected between the first output terminal and the reference potential port. The first LC resonator is configured to compensate for an output capacitance of the RF amplifier at a center frequency of the RF signal. The second LC resonator is configured to compensate for a second order harmonic of the RF signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.