Method and apparatus for manufacturing three-dimensional-structure memory device
US10006121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2014 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Nov 13, 2035 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC23C16/4585
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.