Chip performance monitoring system and method
US10006964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2016 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Apr 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/348
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.