Inventor · South Hero, VT, US

Tad J. Wilder

32Patents

6h-index

50Co-inventors

72Inventor score

Filing activity: Oct 7, 1996 → Nov 3, 2017

Most-cited inventions

Patent	Title	Area	Cited by	Status
US6023567A	Method and apparatus for verifying timing rules for an integrated circuit design	Physics	12	Expired
US7480888B1	Design structure for facilitating engineering changes in integrated circuits	Physics	7	Active
US7305600B2	Partial good integrated circuit and method of testing same	Physics	7	Expired
US8464199B1	Circuit design using design variable function slope sensitivity	Physics	6	Active
US9097765B1	Performance screen ring oscillator formed from multi-dimensional pairings of scan chains	Physics	6	Active
US8086988B2	Chip design and fabrication method optimized for profit	Physics	6	Active
US9128151B1	Performance screen ring oscillator formed from paired scan chains	Physics	4	Active
US8060845B2	Minimizing impact of design changes for integrated circuit designs	Physics	4	Active
US8302063B2	Method and system to optimize semiconductor products for power, performance, noise, and cost through use of variable power supply voltage compression	Physics	4	Active
US8141028B2	Structure for identifying and implementing flexible logic block logic for easy engineering changes	Physics	4	Active
US7302673B2	Method and system for performing shapes correction of a multi-cell reticle photomask design	Physics	3	Expired
US9157956B2	Adaptive power control using timing canonicals	Physics	3	Active
US9188643B2	Flexible performance screen ring oscillator within a scan chain	Physics	3	Active
US9383766B2	Chip performance monitoring system and method	Physics	3	Active
US7543203B2	LSSD-compatible edge-triggered shift register latch	Physics	2	Active
US7478301B2	Partial good integrated circuit and method of testing same	Physics	2	Active
US8754696B2	Ring oscillator	Electricity	2	Active
US7434129B2	Partial good integrated circuit and method of testing same	Physics	2	Active
US9489482B1	Reliability-optimized selective voltage binning	Physics	2	Active
US8341588B2	Semiconductor layer forming method and structure	Physics	2	Active
US9639645B2	Integrated circuit chip reliability using reliability-optimized failure mechanism targeting	Physics	2	Active
US10006964B2	Chip performance monitoring system and method	Physics	1	Active
US8181148B2	Method for identifying and implementing flexible logic block logic for easy engineering changes	Physics	1	Active
US10539611B2	Integrated circuit chip reliability qualification using a sample-specific expected fail rate	Emerging Cross-Sectional Technologies	1	Active
US8381050B2	Method and apparatus for increased effectiveness of delay and transition fault testing	Physics	1	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.