Memory device and system including the same
US10007454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2016 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Feb 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a command controller configured to buffer an address based on a refresh enable signal and a repair enable signal. The memory device may include a fuse circuit configured to control a rupture operation of a refresh cell array and repair cell array corresponding to the address according to the refresh enable signal and the repair enable signal, and output a refresh control signal and a repair control signal during a boot-up operation. The memory device may include a refresh controller configured to control a refresh operation of a bank according to a refresh control signal. The memory device may include a repair controller configured to control a repair operation of the bank according to a redundancy signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.