Multi-threaded translation and transaction re-ordering for memory management units
US10007619B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2015 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Aug 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.