Alexander Miretsky
11Patents
4h-index
21Co-inventors
56Inventor score
Filing activity: Jan 7, 2000 → Sep 25, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6553487B1 | Device and method for performing high-speed low overhead context switch | Physics | 16 | Expired |
| US7409572B1 | Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board | Emerging Cross-Sectional Technologies | 11 | Expired |
| US10007619B2 | Multi-threaded translation and transaction re-ordering for memory management units | Physics | 8 | Active |
| US6647462B1 | Apparatus and a method for providing decoded information | Physics | 5 | Expired |
| US9824015B2 | Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media | Emerging Cross-Sectional Technologies | 3 | Active |
| US7657774B1 | Low power memory controller with leaded double data rate DRAM package on a two layer printed circuit board | Emerging Cross-Sectional Technologies | 3 | Active |
| US10019380B2 | Providing memory management functionality using aggregated memory management units (MMUs) | Physics | 1 | Active |
| US9836410B2 | Burst translation look-aside buffer | Physics | 0 | Active |
| US9785559B2 | Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media | General | 0 | Revoked |
| US9747213B2 | Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media | General | 0 | Revoked |
| US7849256B2 | Memory controller with ring bus for interconnecting memory clients to memory devices | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.