Patent · US Active

Clock generation circuitry for memory applications

US10008260B1 · kind B1 · utility

2Cited by

3References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Bikas Maiti · Austin, US
Rahul Mathur · Austin, US
Sanjay Mangal · Austin, US

Key dates

Filing date	Apr 18, 2017
Grant date	Jun 26, 2018
Priority date	—
Expiry date	Apr 18, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG11C5/14
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to an integrated circuit having level shift circuitry that receives a clock signal in a first voltage domain from a first voltage supply and provides a level shifted clock signal in a second voltage domain based on a second voltage supply that is different than the first voltage supply. The integrated circuit may include clock generator pulse circuitry that receives the clock signal in the first voltage domain from the first voltage supply and receives the level shifted clock signal in the second voltage domain from the level shift circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.