Bikas Maiti
23Patents
10h-index
43Co-inventors
75Inventor score
Filing activity: Aug 31, 1995 → Jul 14, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6020024A | Method for forming high dielectric constant metal oxides | Electricity | 270 | Expired |
| US6027961A | CMOS semiconductor devices and method of formation | Electricity | 192 | Expired |
| US6171910A | Method for forming a semiconductor device | Electricity | 155 | Expired |
| US5861347A | Method for forming a high voltage gate dielectric for use in integrated circuit | Emerging Cross-Sectional Technologies | 136 | Expired |
| US5885870A | Method for forming a semiconductor device having a nitrided oxide dielectric layer | Electricity | 89 | Expired |
| US6049114A | Semiconductor device having a metal containing layer overlying a gate dielectric | Emerging Cross-Sectional Technologies | 56 | Expired |
| US6376349B1 | Process for forming a semiconductor device and a conductive structure | Electricity | 18 | Expired |
| US5830802A | Process for reducing halogen concentration in a material layer during semiconductor device fabrication | Emerging Cross-Sectional Technologies | 17 | Expired |
| US6084279A | Semiconductor device having a metal containing layer overlying a gate dielectric | Electricity | 17 | Expired |
| US6255204A | Method for forming a semiconductor device | Electricity | 16 | Expired |
| US8611172B2 | Controlling a voltage level of an access signal to reduce access disturbs in semiconductor memories | Physics | 2 | Active |
| US9997217B1 | Write assist circuitry | Physics | 2 | Active |
| US10008260B1 | Clock generation circuitry for memory applications | Physics | 2 | Active |
| US10854280B2 | Read assist circuitry for memory applications | Physics | 1 | Active |
| US9064559B2 | Memory device and method of performing access operations within such a memory device | Physics | 1 | Active |
| US11005461B2 | Level shift latch circuitry | Electricity | 0 | Active |
| US11501809B1 | Contention-adapted read-write pulse generation circuitry | Physics | 0 | Active |
| US11664086B2 | Column redundancy techniques | Physics | 0 | Active |
| US8264896B2 | Integrated circuit having an array supply voltage control circuit | Physics | 0 | Active |
| US11967365B2 | Bitcell architecture with time-multiplexed ports | Physics | 0 | Active |
| US10839934B2 | Redundancy circuitry for memory application | Physics | 0 | Active |
| US8116153B2 | Read only memory and method of reading same | Physics | 0 | Active |
| US11475944B2 | Read assist circuitry for memory applications | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.