Semiconductor device having a porous low-k structure
US10008382B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2015 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Jul 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.