Hai-Ching Chen
181Patents
10h-index
70Co-inventors
83Inventor score
Filing activity: May 26, 1987 → Jan 23, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9134633B2 | System and method for dark field inspection | Physics | 60 | Active |
| US4970504A | Security system | Physics | 51 | Expired |
| US9036956B2 | Method of fabricating a polymer waveguide | Physics | 25 | Active |
| US9177797B2 | Lithography using high selectivity spacers for pitch reduction | Electricity | 25 | Active |
| US9659864B2 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Electricity | 21 | Active |
| US4812841A | Computer-controlled password lock | Physics | 18 | Expired |
| US9773676B2 | Lithography using high selectivity spacers for pitch reduction | Electricity | 15 | Active |
| US5004076A | Apparatus for controlling an electric elevator | Performing Operations; Transporting | 13 | Expired |
| US9041015B2 | Package structure and methods of forming same | Electricity | 13 | Active |
| US8264066B2 | Liner formation in 3DIC structures | Electricity | 12 | Active |
| US8440564B2 | Schemes for forming barrier layers for copper in interconnect structures | Electricity | 9 | Active |
| US9941157B2 | Porogen bonded gap filling material in semiconductor manufacturing | Electricity | 8 | Active |
| US7964496B2 | Schemes for forming barrier layers for copper in interconnect structures | Electricity | 7 | Active |
| US8446012B2 | Interconnect structures | Electricity | 7 | Active |
| US8976833B2 | Light coupling device and methods of forming same | Electricity | 7 | Active |
| US9818690B2 | Self-aligned interconnection structure and method | Electricity | 7 | Active |
| US7682963B2 | Air gap for interconnect application | Electricity | 7 | Active |
| US9230911B2 | Interconnect structure and method of forming the same | Electricity | 6 | Active |
| US8729703B2 | Schemes for forming barrier layers for copper in interconnect structures | Electricity | 6 | Active |
| US7928549B2 | Integrated circuit devices with multi-dimensional pad structures | Electricity | 6 | Active |
| US8735278B2 | Copper etch scheme for copper interconnect structure | Electricity | 6 | Active |
| US10008382B2 | Semiconductor device having a porous low-k structure | Electricity | 5 | Active |
| US10014175B2 | Lithography using high selectivity spacers for pitch reduction | Electricity | 5 | Active |
| US8232201B2 | Schemes for forming barrier layers for copper in interconnect structures | Electricity | 5 | Active |
| US9335473B2 | Package structure and methods of forming same | Electricity | 5 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.