Methods of manufacturing vertical memory devices at an edge region
US10008389B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2017 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Jan 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a vertical memory device includes forming a preliminary first mold structure on a substrate, which includes main and edge regions, and the first preliminary mold structure including alternating insulation and sacrificial layers, forming a first mask on the preliminary first mold structure to expose the preliminary first mold structure between a boundary of the substrate and a first target position, partially etching the insulation and sacrificial layers using the first mask to form a preliminary second mold structure, forming a second mask on the preliminary second mold structure to expose the preliminary second mold structure between the boundary of the substrate and a second target position different from the first target position, and partially etching the insulation layers and the sacrificial layers using the second mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.