Jae-Joo Shim
24Patents
8h-index
47Co-inventors
71Inventor score
Filing activity: Aug 5, 2005 → Feb 10, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8284601B2 | Semiconductor memory device comprising three-dimensional memory cell array | Electricity | 35 | Active |
| US8921918B2 | Three-dimensional semiconductor devices | Electricity | 23 | Active |
| US8809938B2 | Three dimensional semiconductor memory devices | Electricity | 18 | Active |
| US8787082B2 | Semiconductor memory device comprising three-dimensional memory cell array | Electricity | 16 | Active |
| US8519472B2 | Semiconductor device and method of forming the same | Electricity | 16 | Active |
| US7825472B2 | Semiconductor device having a plurality of stacked transistors and method of fabricating the same | Electricity | 14 | Active |
| US8592912B2 | Semiconductor device and method of fabricating the same | Electricity | 12 | Active |
| US9111799B2 | Semiconductor device with a pick-up region | Electricity | 10 | Active |
| US8742466B2 | Three-dimensional semiconductor device including a mold structure providing gap regions and an interconnection structure including a plurality of interconnection patterns formed in the gap regions | Electricity | 7 | Active |
| US8563378B2 | Manufacturing semiconductor devices | Electricity | 7 | Active |
| US8836020B2 | Vertical nonvolatile memory devices having reference features | Electricity | 6 | Active |
| US7276421B2 | Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby | Electricity | 4 | Expired |
| US9209244B2 | Semiconductor device with vertical structures that penetrate conductive patterns and interlayer insulating patterns | Electricity | 2 | Active |
| US9196525B2 | Three-dimensional semiconductor device and method of fabricating the same | Electricity | 2 | Active |
| US11495615B2 | Three-dimensional semiconductor memory device | Physics | 2 | Active |
| US7927932B2 | Semiconductor device having a plurality of stacked transistors and method of fabricating the same | Electricity | 1 | Active |
| US10008389B2 | Methods of manufacturing vertical memory devices at an edge region | Electricity | 1 | Active |
| US9418911B2 | Three-dimensional semiconductor memory device having sidewall and interlayer molds | Electricity | 1 | Active |
| US7135746B2 | SRAM cells having landing pad in contact with upper and lower cell gate patterns and methods of forming the same | Emerging Cross-Sectional Technologies | 1 | Expired |
| US7276404B2 | Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns | Emerging Cross-Sectional Technologies | 1 | Active |
| US10790294B2 | Vertical memory device | Electricity | 1 | Active |
| US10784281B2 | Three-dimensional semiconductor memory devices | Electricity | 0 | Active |
| US10825830B2 | Vertical semiconductor devices | Electricity | 0 | Active |
| US12310016B2 | Semiconductor device and electronic system including the same | General | 0 | Revoked |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.