Methods of manufacturing semiconductor devices including conductive structures
US10008407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2015 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Dec 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1047
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.