Fabricating method for wafer-level packaging
US10008478B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 24, 2015 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Nov 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/20642
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip, and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.