Semiconductor device
US10008592B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2017 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Nov 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0297
Abstract
Each first p+-type region is provided between adjacent trenches embedded with a MOS gate and is in contact with a p-type base region. Second p+-type regions face a bottom and bottom corner portions of the trenches in a depth direction. An n-type CS region is a current spread layer provided between the first p+-type regions and the second p+-type regions. The n-type CS region is provided only in an active region and an end thereof is positioned at a boundary of the active region and an edge termination region. Further, the n-type CS region extends to be flush with or farther inward than an outermost first p+-type region. An outermost p++-type contact region extends from a drop between the active region and the edge termination region to the edge termination region and extends beyond the n-type CS region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.