Dual channel transistor
US10008614B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2017 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Mar 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A dual channel transistor includes a first gate electrode, a second gate electrode, a first gate insulation layer, a second gate insulation layer, a silicon semiconductor channel layer, and an oxide semiconductor channel layer. The first gate insulation layer is disposed on the first gate electrode. The silicon semiconductor channel layer is disposed on the first gate insulation layer. The oxide semiconductor channel layer is disposed on the silicon semiconductor channel layer. The second gate insulation layer is disposed on the oxide semiconductor channel layer. The second gate electrode is disposed on the second gate insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.