Alignment of samples across different clock domains
US10009032B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 2, 2017 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Jun 2, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments include systems and methods for providing reliable and precise sample alignment across different clock domains. Some embodiments operate in context of microprocessor power management circuits seeking correlated measurements of voltage droop (VD) and phase delay (PD). For example, a rolling code is generated for each of multiple second clock domain sample times (CDSTs). VD and the rolling code are both sampled according to a first clock domain to generate VD samples and corresponding VCode samples for each of multiple first CDSTs. PD can be sampled according to the second clock domain to generate PD samples for each of the second CDSTs, each associated with the rolling code for its second CDST. For any first CDST, the VD sample for the first CDST can be aligned with a PD sample for a coinciding second CDST by identifying matching associated rolling codes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.