Bruce E. Petrick
16Patents
9h-index
8Co-inventors
65Inventor score
Filing activity: Dec 20, 1984 → Jun 2, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5892966A | Processor complex for executing multimedia functions | Emerging Cross-Sectional Technologies | 84 | Expired |
| US6148391A | System for simultaneously accessing one or more stack elements by multiple functional units using real stack addresses | Physics | 59 | Expired |
| US4646355A | Method and apparatus for input picture enhancement by removal of undersired dots and voids | Physics | 35 | Expired |
| US4648119A | Method and apparatus for forming 3.times.3 pixel arrays and for performing programmable pattern contingent modifications of those arrays | Physics | 28 | Expired |
| US5872965A | System and method for performing multiway branches using a visual instruction set | Physics | 28 | Expired |
| US4648026A | Microprocessor stepper motor drive | Physics | 18 | Expired |
| US5920889A | Apparatus and method for write miss processing in a copy-back data cache with an allocating load buffer and a non-allocating store buffer | Physics | 13 | Expired |
| US5715425A | Apparatus and method for prefetching data into an external cache | Physics | 11 | Expired |
| US6446168B1 | Method and apparatus for dynamically switching a cache between direct-mapped and 4-way set associativity | Physics | 10 | Expired |
| US8205110B2 | Synchronous operation of a system with asynchronous clock domains | Physics | 8 | Active |
| US6334180A | Processor coupled by visible register set to modular coprocessor including integrated multimedia unit | Physics | 5 | Expired |
| US5856746A | Logic speed-up by selecting true/false combinations with the slowest logic signal | Electricity | 3 | Expired |
| US8103888B2 | Method and apparatus for power savings in a multi-threaded processor using a symbol gated with a clock signal | Emerging Cross-Sectional Technologies | 1 | Active |
| US9705509B1 | Alignment of samples across different clock domains | Physics | 1 | Active |
| US10009032B2 | Alignment of samples across different clock domains | Physics | 0 | Active |
| US8848576B2 | Dynamic node configuration in directory-based symmetric multiprocessing systems | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.