Patent · US Active

Partner-aware virtual microsectoring for sectored cache architectures

US10013352B2 · kind B2 · utility

2Cited by

2References

17Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Sreenivas Subramoney · Bengaluru, IN
Jayesh Gaur · Bengaluru, IN
Mukesh Agrawal · Bengaluru, IN
Mainak Chaudhuri · Kanpur, IN

Key dates

Filing date	Sep 26, 2014
Grant date	Jul 3, 2018
Priority date	—
Expiry date	Sep 26, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/3042
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at least one hardware processor core and a sectored dynamic random access (DRAM) cache coupled to the at least one hardware processor core.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.