Inventor · Bengaluru, IN

Jayesh Gaur

30Patents
3h-index
57Co-inventors
62Inventor score

Filing activity: Apr 1, 2011 → Jan 24, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US11575504B2 Cryptographic computing engine for memory load and store units of a microarchitecture pipeline Electricity 5 Active
US10915421B1 Technology for dynamically tuning processor features Physics 3 Active
US12028094B2 Application programming interface for fine grained low latency decompression within processor core Physics 3 Active
US10331582B2 Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time Physics 2 Active
US10754655B2 Automatic predication of hard-to-predict convergent branches Physics 2 Active
US10013352B2 Partner-aware virtual microsectoring for sectored cache architectures Physics 2 Active
US12086591B2 Device, method and system to predict an address collision by a load and a store Physics 2 Active
US10268600B2 System, apparatus and method for prefetch-aware replacement in a cache memory hierarchy of a processor Physics 2 Active
US8667222B2 Bypass and insertion algorithms for exclusive last-level caches Physics 2 Active
US10176099B2 Using data pattern to mark cache lines as invalid Physics 2 Active
US10719355B2 Criticality based port scheduling Physics 1 Active
US10866902B2 Memory aware reordered source Physics 1 Active
US10496413B2 Efficient hardware-based extraction of program instructions for critical paths Physics 1 Active
US10162756B2 Memory-efficient last level cache architecture Physics 1 Active
US10846093B2 System, apparatus and method for focused data value prediction to accelerate focused instructions Physics 0 Active
US11256599B2 Technology for dynamically tuning processor features Physics 0 Active
US9251096B2 Data compression in processor caches Physics 0 Active
US10956327B2 Systems and methods for mitigating dram cache conflicts through hardware assisted redirection of pages (HARP) Physics 0 Active
US11972126B2 Data relocation for inline metadata Physics 0 Active
US11656971B2 Technology for dynamically tuning processor features Physics 0 Active
US11043256B2 High bandwidth destructive read embedded memory Physics 0 Active
US9292449B2 Cache memory data compression and decompression Physics 0 Active
US10776270B2 Memory-efficient last level cache architecture Physics 0 Active
US11188467B2 Multi-level system memory with near memory capable of storing compressed cache lines Emerging Cross-Sectional Technologies 0 Active
US9720829B2 Online learning based algorithms to increase retention and reuse of GPU-generated dynamic surfaces in outer-level caches Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.