Control device for controlling semiconductor memory device
US10014035B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2017 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Aug 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control device includes: a dummy memory cell group; a transistor having a first terminal, a grounded second terminal and a control terminal; an adjustor providing a resistance between the dummy memory cell group and the first terminal of the transistor; an inverter generating, based on a voltage at the first terminal of the transistor, a sense start signal that is associated with switching of a sense amplifier circuit of a semiconductor memory device from a disabled state to an enabled state; and a controller generating, based on the sense start signal, a control signal for controlling the transistor such that switching of the transistor from conduction into non-conduction is associated with the sense start signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.