Low power and area efficient memory receiver
US10014036B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2016 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Jan 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of a receiver apparatus may include high pass components to pass high frequency components of an input signal, low pass components to pass low frequency components of the input signal, and an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components, wherein the low pass components include a level shifter to shift a common mode voltage level of the input signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices. Other embodiments are disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.