Non-volatile semiconductor storage device
US10014064B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2017 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Mar 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.