3D semiconductor device and structure
US10014292B2 · kind B2 · utility
55Cited by
0References
20Claims
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Key dates
| Filing date | Apr 2, 2017 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Apr 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/18
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D semiconductor device, the device including: a first die including a first transistors layer and a first interconnection layer; and a second die overlaying the first die, the second die including a second transistors layer and a second interconnection layer, where the second die thickness is less than 2 microns, and where the first die is substantially larger than the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.