Transient voltage suppression devices with symmetric breakdown characteristics
US10014388B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2017 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Jan 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.