Victor Torres
20Patents
5h-index
30Co-inventors
69Inventor score
Filing activity: Oct 8, 1999 → Jan 10, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7410879B1 | System and method for providing a dual via architecture for thin film resistors | Electricity | 22 | Expired |
| US7332403B1 | System and method for providing a buried thin film resistor having end caps defined by a dielectric mask | Electricity | 14 | Expired |
| US7115500B1 | System and method for providing a dry-wet-dry etch procedure to create a sidewall profile of a via | Electricity | 11 | Expired |
| US6306675A | Method for forming a low-defect epitaxial layer in the fabrication of semiconductor devices | Electricity | 11 | Expired |
| US7456097B1 | System and method for faceting via top corners to improve metal fill | Electricity | 6 | Expired |
| US9279192B2 | Method for manufacturing SiC wafer fit for integration with power device manufacturing technology | Electricity | 5 | Active |
| US7585775B1 | System and method for faceting a masking layer in a plasma etch to slope a feature edge | Electricity | 4 | Expired |
| US7808048B1 | System and method for providing a buried thin film resistor having end caps defined by a dielectric mask | Electricity | 3 | Active |
| US10002760B2 | Method for manufacturing SiC wafer fit for integration with power device manufacturing technology | Electricity | 3 | Active |
| US8765091B2 | Method to manufacture large uniform ingots of silicon carbide by sublimation/condensation processes | Chemistry; Metallurgy | 2 | Active |
| US7172973B1 | System and method for selectively modifying a wet etch rate in a large area | Electricity | 2 | Expired |
| US7960240B1 | System and method for providing a dual via architecture for thin film resistors | Electricity | 0 | Active |
| US10354871B2 | Sputtering system and method for forming a metal layer on a semiconductor device | Electricity | 0 | Active |
| US10014388B1 | Transient voltage suppression devices with symmetric breakdown characteristics | Electricity | 0 | Active |
| US10969409B2 | Miniaturized current sensors | Electricity | 0 | Active |
| US11245003B2 | Systems and methods for junction termination of wide band gap super-junction power devices | Electricity | 0 | Active |
| US10741551B2 | Integrated vertical and lateral semiconductor devices | Electricity | 0 | Active |
| US11764257B2 | Systems and methods for junction termination of wide band gap super-junction power devices | Electricity | 0 | Active |
| US11986588B2 | Electronic system | Electricity | 0 | Active |
| US11271076B2 | Systems and methods for junction termination in semiconductor devices | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.