Modular system on chip configuration system
US10019546B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 2015 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Mar 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0766
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-a-chip (SoC) includes a master module and a first adapter module. The master module includes an upstream interface and a downstream interface. The upstream interface is coupled to a host unit for receiving a write burst or a read burst therefrom. The master module is configured to convert the write burst or the read burst into a series of access requests to the downstream interface. The first adapter module includes an input interface, an output interface, and an endpoint interface, and an address Base Address Register (BAR). The input interface is coupled to the downstream interface of the master module. The output interface is coupled to a second adapter module or to a termination module. The endpoint interface is coupled to a first functional unit or to a third adapter module. The first adapter module is configured to detect a respective access request corresponding to the address BAR.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.