Inventor · Nofit, IL

Gil Stoler

30Patents
8h-index
19Co-inventors
72Inventor score

Filing activity: Dec 23, 1996 → Nov 30, 2018

Most-cited inventions

PatentTitleAreaCited byStatus
US7245627B2 Sharing a network interface card among multiple hosts Electricity 188 Expired
US7149227B2 Round-robin arbiter with low jitter Electricity 91 Expired
US7224669B2 Static flow rate control Electricity 26 Expired
US9628211B1 Clock generation with non-integer clock dividing ratio Electricity 19 Active
US8332590B1 Multi-stage command processing pipeline and method for shared cache access Physics 17 Active
US8117395B1 Multi-stage pipeline for cache access Physics 16 Active
US10691576B1 Multiple reset types in a system Physics 12 Active
US7652516B2 Apparatus and method for generating a clock signal Physics 11 Active
US5764932A Method and apparatus for implementing a dual processing protocol between processors Physics 6 Expired
US10746792B1 Debug mechanisms for a processor circuit Physics 5 Active
US10019546B1 Modular system on chip configuration system Physics 5 Active
US7932768B2 Apparatus and method for generating a clock signal Physics 5 Active
US10185678B1 Universal offloading engine Physics 5 Active
US10078568B1 Debugging a computing device Physics 5 Active
US9800400B1 Clock phase alignment in data transmission Electricity 4 Active
US8089378B1 Synchronous multi-clock protocol converter Electricity 3 Active
US9141546B2 System and method for managing transactions Physics 3 Active
US9411731B2 System and method for managing transactions Physics 2 Active
US8499123B1 Multi-stage pipeline for cache access Physics 1 Active
US8938585B1 Transparent processing core and L2 cache connection Physics 1 Active
US10061700B1 System and method for managing transactions Physics 1 Active
US8954681B1 Multi-stage command processing pipeline and method for shared cache access Physics 0 Active
US8688911B1 Transparent processing core and L2 cache connection Physics 0 Active
US10635589B2 System and method for managing transactions Physics 0 Active
USRE46766E1 Cache pre-fetch architecture and method General 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.